1. Field of the Invention
This invention relates to a method and apparatus for writing and reading data to/from a memory, and particularly to a method and apparatus for writing and reading data to/from a memory which has memory areas arranged in the form of a matrix.
2. Description of the Related Art
A recent information processing system incorporates, in order to perform optimal data processing, a first CPU for processing data of long bit-length (e.g., 16-bit words) and a second CPU for processing data of short bit-length (e.g., 4-bit words), so that it operates with the two CPUs selectively depending on the contents of individual processings. In this case, when 16-bit word data processed by the first CPU is stored in a first-in-first-out (FIFO) memory having memory areas in a matrix arrangement, as disclosed in Japanese Patent JP-A-58-53255 for example, and thereafter the stored data is processed by the second CPU, it is necessary to convert the 16-bit word data into 4-bit word data. However, since the memory does not have such a bit-length converting function, it is required to provide four FIFO memories, each having 4-bit memory areas, and a bus exchanger so that each 16-bit word processed by the first CPU is divided into four 4-bit words, which are stored respectively, in associated areas of the four memories, and the stored words are read out of the memories in series and then processed by the second CPU. On the other hand, when 4-bit words, which have been processed by the second CPU, are to be processed by the first CPU, four of the 4-bit words are fed through the bus exchanger and stored in the associated areas of the four memories so that the stored four 4-bit words are read out in parallel to form a 16-bit word, which is processed by the first CPU. The above-mentioned memory utilization is disclosed in Japanese Patent JP-A-56-101261 for example.
However, this data processing for bit-length conversion from four 4-bit words into a 16-bit word, and vice versa, by using a bus exchanger involves the problem of taking excessive processing time, resulting in a degraded throughput of the whole system. Another problem is its intricate hardware configuration, which results in a limited performance.